
module PhaseMemory(
  input  wire        clk,
  input  wire        rst_n,
  input  wire [ 4:0] slot,
  input  wire        memwr,
  input  wire [17:0] memin,
  output reg  [17:0] memout
);

reg[17:0] phase_array_00;
reg[17:0] phase_array_01;
reg[17:0] phase_array_02;
reg[17:0] phase_array_03;
reg[17:0] phase_array_04;
reg[17:0] phase_array_05;
reg[17:0] phase_array_06;
reg[17:0] phase_array_07;
reg[17:0] phase_array_08;
reg[17:0] phase_array_09;
reg[17:0] phase_array_10;
reg[17:0] phase_array_11;
reg[17:0] phase_array_12;
reg[17:0] phase_array_13;
reg[17:0] phase_array_14;
reg[17:0] phase_array_15;
reg[17:0] phase_array_16;
reg[17:0] phase_array_17;

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_00 <= #1 18'b0;
    else if(memwr && (slot==5'd0))
	phase_array_00 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_01 <= #1 18'b0;
    else if(memwr && (slot==5'd1))
	phase_array_01 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_02 <= #1 18'b0;
    else if(memwr && (slot==5'd2))
	phase_array_02 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_03 <= #1 18'b0;
    else if(memwr && (slot==5'd3))
	phase_array_03 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_04 <= #1 18'b0;
    else if(memwr && (slot==5'd4))
	phase_array_04 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_05 <= #1 18'b0;
    else if(memwr && (slot==5'd5))
	phase_array_05 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_06 <= #1 18'b0;
    else if(memwr && (slot==5'd6))
	phase_array_06 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_07 <= #1 18'b0;
    else if(memwr && (slot==5'd7))
	phase_array_07 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_08 <= #1 18'b0;
    else if(memwr && (slot==5'd8))
	phase_array_08 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_09 <= #1 18'b0;
    else if(memwr && (slot==5'd9))
	phase_array_09 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_10 <= #1 18'b0;
    else if(memwr && (slot==5'd10))
	phase_array_10 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_11 <= #1 18'b0;
    else if(memwr && (slot==5'd11))
	phase_array_11 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_12 <= #1 18'b0;
    else if(memwr && (slot==5'd12))
	phase_array_12 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_13 <= #1 18'b0;
    else if(memwr && (slot==5'd13))
	phase_array_13 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_14 <= #1 18'b0;
    else if(memwr && (slot==5'd14))
	phase_array_14 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_15 <= #1 18'b0;
    else if(memwr && (slot==5'd15))
	phase_array_15 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_16 <= #1 18'b0;
    else if(memwr && (slot==5'd16))
	phase_array_16 <= #1 memin;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	phase_array_17 <= #1 18'b0;
    else if(memwr && (slot==5'd17))
	phase_array_17 <= #1 memin;
end

always @(*)begin
    case(slot)
    5'd0   : memout = phase_array_00;
    5'd1   : memout = phase_array_01;
    5'd2   : memout = phase_array_02;
    5'd3   : memout = phase_array_03;
    5'd4   : memout = phase_array_04;
    5'd5   : memout = phase_array_05;
    5'd6   : memout = phase_array_06;
    5'd7   : memout = phase_array_07;
    5'd8   : memout = phase_array_08;
    5'd9   : memout = phase_array_09;
    5'd10  : memout = phase_array_10;
    5'd11  : memout = phase_array_11;
    5'd12  : memout = phase_array_12;
    5'd13  : memout = phase_array_13;
    5'd14  : memout = phase_array_14;
    5'd15  : memout = phase_array_15;
    5'd16  : memout = phase_array_16;
    5'd17  : memout = phase_array_17;
    default: memout = phase_array_00;
    endcase	    
end	

endmodule
